• Exceptions levels in the ARMv8 architecture
    Hello There are four exceptions levels in the ARMv8 architecture. EL0 EL1 EL2 EL3 Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure...
  • Exception Level Switch in ARMv8
    HI there: i am developing on a ARMv8 a57 based CPU, i want to disable the cache mechanism. it seems i need the access the corresponding registers in EL1 or above. i wonder how could i switch the EL...
  • Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?
    I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single...
  • Reset Management Register Functioanlity in ARM v8
    Hi Experts, Does the Reset Management Register will be implemented mandatory or optional for the SoC based on ARMv8 and how it is practically used ? Regards, Techguyz
  • Armv8 Memory Mapping
    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which...