• AXI3 data interleaving
    Hi, I was going through write data interleaving section in ARM AXI3 protocol. Found this statement: "For a slave that supports write data interleaving, the order in which it receives the first data item...
  • Use-cases of AXI3 unaligned transfers
    Hi all, I cannot think of a good usecase of unaligned transfers in AXI3. - For unaligned write, a master can anyway use aligned write + write strobes. - For unaligned read, a master can use aligned...
  • AXI Wrap Bursts
    In case of wrapped bursts, we need to calculate first the Aligned_Address, using: Suppose start address is 55, assuming 32 - bit bus, burst length of 4 Aligned_Address = (INT(Start_Address / Number_Bytes...
  • Reason for having decouple write address, data channels in AXI4
    Can someone explain me the advantage of having decouple write address, data channels in AXI4? In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of...
  • Question about AXI Wrapping burst
    There is a statement ' For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers. ' in AXI Addressing option. I cannot understand that why must be 2,4,8 or 16 transfers? Is there some...