• The Top 5 Things to Know about Cortex-A53
    The Arm Cortex-A53 was introduced to the market in October 2012, delivering the Armv8 instruction set and significantly increased performance in a highly efficient power and area footprint. It is available...
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...
  • Cortex-A53 processor instruction cycles
    hi , I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies...
  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process
    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix...
  • Why the address width of MMU-500 is different with Cortex-A53/57?
    I find the description below from MMU-500 TRM. Address width The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address...