• Alignment in ARM?
    I could not clearly understand the alignment issues present in ARM. Sometimes I get BUS ERROR while running an assembly file but don't know how to resolve it. Some of the doubts: 1. Is it better to store...
  • Can anyone provide an example of asynchronous exceptions?
    Below is from ARMv7 Architecture doc.           An exception is described as asynchronous if either of the following applies:           — the exception is not generated as a result of direct execution...
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM
    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...
  • Division by non-power-of-2 hits into exception
    Hi there, I was using Codewarrior targeting Cortex-R4 CPU to build Firmware. When doing a division coprocessor was used and caused exception. Here is the division in C: u8 i, j = 8; i = j / 3; Disassembly...
  • VTTBR_EL2 alignment
    Hi folks, in Armv8 reference manual, in the description of the VTTBR_EL2 register, the BADDR fields seems to have alignment constraints: Translation table base address, bits[47:x]. Bits [x-1:0] are RES...