• Enable MMU and d-cache on ARMv8 for u-boot
    Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...
  • ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...
  • armv7a/armv8 : Undefined Abort Exception and MMU
    Hi ! When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before...
  • determine a page size on armv8
    Hi, I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of __asm__ volatile ("at s1e1r, %0" : : "r" (buf)); __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r"...
  • Trouble configuring MMU for 2MB block mapping
    So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...