• instructions fetch
    Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
  • Cache Allocation Technology
    Hi guys, I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process...
  • ARMv7 CortexA9 Cache Policy - No allocate ?
    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A...
  • unaligned data fetch in Cortexa9
    I have a question related to data fetch, when on gdb debugger I do an address read say as: X 0x81000000 Then it will fetch 64 bits as you told in reference to Cortex A9 If further I do X 0x81000004 Will...
  • Disabling PFU / instruction pre-fetch on Cortex-R4?
    Hello, I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me: Determines if instructions can...