• Cache Coherence
    Hi ,    I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.    1. Bring Core 1 out of reset.    2. Bring Core 2 out of reset.    3. Invalidate...
  • Cache coherency in big.little system.
    Within an arm system, a cluster is an ACE master connected to the Arm CCI. To keep the cache coherency, the cluster would send some transactions to the bus and are trapped by the snoop filter of CCI....
  • Trustzone and caches
    Hi, this question is following my work on the PL310 L2 cache of an imx6 board (see The specified item was not found. ). We are developing a secure OS that will run alongside Linux. At boot, our secure...
  • Multi core L1 cache coherent
    Dear experts, I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation. Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached)...
  • Cache Allocation Technology
    Hi guys, I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process...