• Is Cache Stashing introduced in DynamIQ similar to IO coherency?
    IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to...
  • ARMv8 memory ordering
    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code: AArch32 Px PLDW[R1] ; preload into cache in unique state Loop...
  • Does Cortex-M0+ has a flash patch mechanism similar to the FPB function of Cortex-M4?
    Hello, As shown in title, does cortex-m0+ has flash patch and break point(FPB) function similar to cortex-m4, which will facilitate the upgrading of ROM code in the form of hardware. Thanks
  • Armv8 Memory Mapping
    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which...
  • ARMv8-A CurrentEL Register Definition
    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM. . How does the PSTATE bits map to CurrentEL ? I...