• How long does it take for Cortex A53 to exit low power state?
    Hi, The ARMv8A architecture profile shared an example of using WFE in the implementation of spinlock. I'd like to know how long it might take for Cortex A53 to exit from lower power state. If it is...
  • Program Counter in Cortex-M0
    Hi, my question sounds trivial, but I just cannot find the register for the program counter in my Cortex-M0. According to the Register TRM it should be R15, which is not available in the GPR module...
  • About watch point debug excption on Cortex-A53
    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler. In our watch point handler...
  • Pipeline Stages in the Cortex-A53
    Hi I am a student. I was looking into the cortex A53 and found that it has 8 pipeline stages. However, I am unable to find the detailed functioning of each stage after a lot of browsing. I need information...
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...