• Best way to safely check if virtual address exists
    Hello, I'm trying to, given a virtual address, quickly check if it exists (if it is mapped) to know if I can access it in a safe way, without generating an exception. I'm currently using the AT instruction...
  • STRD ATOMIC?
    Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system). Question. Is 64bit-aligned STRD(64bit memory access) atomic ? (I know tha It is not atomic, but i don't know behavior.) For...
  • Enable and disable MMU page table caching in L2
    Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
  • Permission fault, level 2 on MMU enable
    Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish: 4GiB space, 4kiB...
  • Enable MMU and d-cache on ARMv8 for u-boot
    Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...