• Arm a53: Populate TLB without table walk?
    Hi, From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk. Good starting point. But, should I access the same memory location again, it won...
  • Cortex-A9 TLB lockdown
    Hello, expert. I tried to implement TLB lockdown in Cortex-A9. Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it. I tried TLB lockdown following Cortex...
  • Count Main TLB miss
    Hello, experts: My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6). I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss. But PMUEVENT doesn't support the main TLB miss...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • How machine learning at the edge is helping to save Rudolph this Christmas
    Obviously, Father Christmas – or Santa Claus or whatever else he’s known as – is real. Whoever tells you otherwise is either misinformed or simply a liar. However, he can only deliver all of the presents...