• A53 - MMU vs MPU
    Do Arm offer A53 with only MPU? Because right now we have only one to one mapping. we just need to use MPU only. Yes I understand MMU is superset of MPU but can be expensive (performance wise). Or there...
  • making physical memory pages not cacheable (probabaly by modifying page table entry)
    I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
  • Enable and disable MMU page table caching in L2
    Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
  • Page Colouring on ARMv6 (and a bit on ARMv7)
    Page colouring is a technique for allocating pages for an MMU such that the pages exist in the cache in a particular order. The technique is sometimes used as an optimization (and is not specific to...
  • Is it necessary to flush data cache of a modified page table entry?
    Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...