• Is it necessary to flush data cache of a modified page table entry?
    Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...
  • determine a page size on armv8
    Hi, I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of __asm__ volatile ("at s1e1r, %0" : : "r" (buf)); __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r"...
  • ARM A64 Page table
    Hi, I have a question on ARM page table. I am running a bare metal application on Cortex A72 and i have a failure with my application. Upon debugging the failure, i found an address which is contributing...
  • Why does Arm still support short descriptors?
    What I'm asking is ARM Architecture Reference Manual for ARMv8-A says in AArch32 there are two translation table formats: Short descriptors: 32 bit Long descriptors: 64 bit On page G4-4726...
  • can anyone tell me the difference between pipelined bus and depipelined bus?and i have uploaded two screen shot of both so what does that arrow from mclk to a[31:0] indicates?
    what does that arrow indicates(arrow from mclk to a[31:0] ?