• Invalid entry - mmu page tables
    Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
  • making physical memory pages not cacheable (probabaly by modifying page table entry)
    I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
  • Count Main TLB miss
    Hello, experts: My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6). I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss. But PMUEVENT doesn't support the main TLB miss...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • Cortex-A9 TLB lockdown
    Hello, expert. I tried to implement TLB lockdown in Cortex-A9. Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it. I tried TLB lockdown following Cortex...