• ARM1136: why the mismatch between cache stalls and cache misses ??
    Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
  • How to compute a cache size?
    It might be a typo in the site, infocenter.arm.com/.../index.jsp . It should be 64KB (not 32KB) based on the picture. > Index (# of lines): 2^8 > # of Words per line: 2^4 > # of Bytes per word: 2^2...
  • How get ARMv7 cache size
    Hi everybody!! I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15). In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the...
  • Cortex-A7 cache line size
    Hi All, when I read the ARM® Cortex -A Series Programmer’s Guide for ARMv7-A I found that at page 8-12 Tabel 8-1 Cache features of Cortex-A series processors (continued) there is a field say that...
  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?
    Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is:...