• Lock-Step mode execution on Cortex-R5
    Dear Forum, Could some one please elaborate on , 1. what is Lock-Step Mode ? 2. What is the General HW configuration required ? 3. How to make a program/application executable in Lock-Step mode ? - In...
  • Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
  • How to test " Lock-Step " is working on Cortex-R5 ?
    Dear Forum, How to test " Lock-Step " is working on Cortex-R5? Please provide inputs on Testing this feature. Thanks, Ravinder Are
  • How to realise a dual-core "LOCK-STEP" Cortex-M7 at the integration level?
    Is here any detail information or integration guide? how to realise the compare logic ,only to compare the CM7 core interface?
  • Can Cortex-A53 be used in lock-step mode?
    Can Cortex-A53 be used in lock-step mode? There are many references for Cortex-R5 being used in lock step mode , could not find any information about Cortex-A53 , Can you please help