• Cortex-R4: Need a explanation for dual-issue restriction
    Hello, The following table is extracted from the Cortex-R4 whitepaper: Could someone help me to explain that question: My concern is that Cortex-R4 can take MOV as first instruction, ADD as second instruction...
  • Very Urgent :VIC in ARM Cortex R4
    Hi all, It was nice experience working with NXP with my favorite S32K1XX series having ARM Cotex M-4 and M-0+. Now i switched to BCM895XX series with ARM Cotex R-4 having VIC for interrupt contolling...
  • Bit scan Instruction ARM cortex R4
    Hi all, I need help for to convert logic in following way: if 1st bit set in (00000000000000000000000000001) i can get 1 f 1st bit set in (00000000000000000000000000100) i can get 2 f 1st bit...
  • IOC flag at FPSCR register
    I using Cortex-R4. And I reading "Cortex™-R4 and Cortex-R4F Technical Reference Manual(Revision:r1p3)". In my system,  IOC flag in FPSCR register is set with unexpected processing. What is the condition...
  • What's the difference between ETM and Debug?
    In the ARM core such as cortex-R4, it has ETM and Debug so I want ask What's the difference between ETM and Debug?