• How to test " Lock-Step " is working on Cortex-R5 ?
    Dear Forum, How to test " Lock-Step " is working on Cortex-R5? Please provide inputs on Testing this feature. Thanks, Ravinder Are
  • Can we inspect contents of the return stack to get the call tree?
    Using Cortex-R5F, I would like to get the contents of the 4-entry call-return stack (i.e. get the addresses). Is this possible through some indirect manner? The goal here is to have the knowlege of...
  • What is the priority between synchronous data abort and FIQ in Cortex-R5F?
    Hi, With Cortex-R5F, we have a case where a read to the L2 memory generates both a synchronous data abort and an FIQ with near-zero delay. We are reading from RAM while the RAM is in test mode and...
  • TCM arbitration hazard: Considerations for Firmware
    According to the ARM spec (ARM DDI 0460D section 8.4.4): TCM arbitration Each TCM port receives requests from the LSU, PFU, and AXI slave. In most cases, the LSU has the highest priority, followed...
  • ARM Cortex-R5 based Lock-step feature demonstration real time application?
    Dear Arm community, is there any real-time application to demonstrate the R5-lock step feature. other than Error injection in to the test register ? Thanks, Ravinder Are