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    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Which ARMv8 register controls cache partitioning
    Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
  • Cache Memory Requirement
    Hi Experts, How to derive the cache memory requirement for the working of the software ? I could understand that each of the A/M/R processors have its own applications and build with its own Cache size...
  • CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support
    Hi, XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features:   - CAT Cache Allocation Technology   - CDP Code and Data Prioritization Those features are supported by x86 L3 caches...
  • Cache type and cache operation sequence
    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC. SW on each execution units (A and B) Reads and Writes to this shared...