• Cortex M4: Atomic and Cache
    Hello all, Recently I came across this issue for the cortex M4 core. We are running a freertos application which loads and stores the value of a variable. For this we are using the atomic functions...
  • Cortex-M4 documentation
    hi, im a total noob here so do excuse if im asking some weird question. im using an arm cortex m4f for the first time ... i looked online and i was able to find the TRM for the arm cortex m4f. however...
  • Cortex M4 - Returning from Interrupt
    Hi, I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get...
  • Prefetch Abort in Cortex M processors
    Hi, We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify...
  • Memory protection unit - Cortex-M4
    Hi. I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS): 1. I enabled background region, thus all...