• cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Cortex-R52 data cache content
    Hi everyone, Is there a way to read the data cache content? I'm using Xilinx SoC ZCU102 evaluation board. Thanks
  • Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)?
    Dear friend    Cortex-M7 has cache. After enable data cache, will data be stored to cache first when I send a large amount of data continually?    The size of data exceed the space of cache.    Thanks...
  • Cortex-A35 cache partitioning
    Hi, I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference...
  • Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...