• Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?
    Hi, I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures. Let's say I have the following assembly, // stuff mrs r0, BASEPRI msr BASEPRI_MAX...
  • arm v7AR debug architecture DCC register access
    Dear sirs, The ARM v7ar manual says that DCC data registers DBGDTRTX and DBGDTRRX have RW attributes from external view. It confuses me why DBGDTRTX can be written from external debugger. what is the...
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?
    Hello guys, I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA. Is ARMv7-M3 instructions compatible to ARMv7-A, especially...
  • mismatch between ARMv7-M ref manual and core_cm7.h
    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h...
  • Updated ARMv7-M architecture reference manual for Cortex-M7 ?
    Has an updated v7m architecture reference been published yet?