• [CM4] Best general way to handle a hardfault/lockup
    Over the past few months I've been doing a lot of work on a Kinetis K24 processor, which is a Cortex-M4, running the MQXLITE RTOS. It also has a couple other SDKs built in and a surprising level of complexity...
  • Can I build my own ARM board like the raspberry pi
    Is it possible and if so how can i build my own raspberry pi alike? Can I use this AM4378 | AM437x | ARM Cortex-A9 | Description & parametrics ???
  • SLVERR from L3 not raised in ISR of ARM PL310 L2 cache controller
    Hello, I am trying to raise L3 SLV interrupts of the ARM PL310 L2 cache controller by generating an AXI slave error on a L2C slave peripheral (which is not DDRC). On my Xilinx Zynq SoC, the ARM PL310...
  • Raising priority of PendSV within NVIC when PendSV pending
    Hi, I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling...
  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?
    Based on ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags...