• Forced Hardfault (INVPC) Exception Error
    Using ARM coretx-M chip set Getting random INVPC hard fault exception error, while running iperf tool for measuring n/w throughput. Hard fault reg: 0x40000000 xPSR: 0x01000000 PRIMASK: 0x00000001...
  • Non-secure EXC_RETURN value to Secure HardFault Handler
    Hi, I have scenario where SCS.AIRCR.BFHFNMINS is the default value of 0, which if I understand correctly means that whenever there is hard-fault, it would be trapped by secure hard-fault handler. ...
  • How to Change the Non Secure VTOR (Cortex-M33)
    Hi, I'm using the Cortex-M33 and I would like to know if it's possible to change the Non Secure Vector table offset address (VTOR) while maintaining the Secure VTOR pointing to a different address....
  • How to place FreeRTOS in secure memory and the user tasks in non-secure memory?
    I am porting FreeRTOS with TrustZone on LPC5500, I put FreeRTOS in secure memory, and created several user tasks in non-secure memory, as shown below: But so far, I have not successfully switched...
  • INVPC Hard fault exception error
    Note: This was originally posted on 16th July 2009 at http://forums.arm.com Using and Arm Cortex M3, the application that is running sometimes will generate a hard fault and deciphering the CFSR register...