• Usage of generic register in CPU reset
    Hi All, Could anyone please tell me which generic register/location in memory can be used for storing a bit value which will not get reset after a CPU reset? I need the register to hold the value after...
  • What is the meaning of a 64 bit aligned stack pointer address?
    According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says: "Although the processor hardware allows SP to be at any word aligned address at function...
  • Cortex-m0 instructions and core registers immediete values
    Hi, i have just got a cortex-m0(LPC1114) based dev board. I'm reading about the architecture and instructions. My understanding is that it supports most thumb 16-bit instructions and a handful thumb-2...
  • Cortex-M0 Thumb-2 instruction: Is this instruction valid?
    STM     r0!, {} I have looked at Thumb2 instruction set web but I can't find the behaviour of STM command if the reglist is empty. Thanks in advance.
  • cortex m0
    The ARMv6-M Architecture Reference Manual for my country is not aviable the dowload from the ARM oficial page, i beginin to stady the cortex M0 if any cand help me whit eny information abuat the micro...