• dsb and dmb
    Hi all: I have some questions about DMB and DSB in armv8. (1) In armv8 Reference Manual doc, it says " The DMB instruction does not ensure the completion of any of the memory accesses for which...
  • What is the difference of DMB and DSB instruction?
    Dear sirs, From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which...
  • Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?
    Hi, I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures. Let's say I have the following assembly, // stuff mrs r0, BASEPRI msr BASEPRI_MAX...
  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?
    Hi Experts, I'm reading white paper for ARMv7 and ARMv8. but when i reading cache part and memory re-ordering, i have silly questions..... Suppose there are below instructions..   Core A:      STR R0...
  • When will be the Release of "The Definitive Guide to Cortex M7" ??
    Hi Sir, may be the title of this question looks fun, but i am eagerly waiting for your next book "The Definitive Guide to Cortex M7" are you working on this book?? When could i Expect this book Thanks...