• ARM Cortex-A9 | Non-cacheable memory range
    Note: This was originally posted on 23rd May 2013 at http://forums.arm.com Hi all, I am designing an application on xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using...
  • Different performance in HYP and SVC mode ARMv7A?
    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident...
  • Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM
    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...
  • If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region?
    If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region? In cortex-A7 spec, it says" the core hardware will check all instruction fetches and...