• Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
  • Correct usage of the NSTable bit in aarch64/armv7a LPAE
    I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that...
  • Launching bare-metal firmware at EL2 (Hyp) on QEMU with ARM Trusted Firmware?
    Hi experts, I am recently developing some bare-metal code for a Cortex-A57 Aarch64 on QEMU (Virt platform) for playing with the Virtualization Extension. I first used one core and I developed a bootloader...
  • I cannot write the sp register in the monitor mode
    I use a Cortex-A7 board and write start up code. I try to use Security Extension. I use `smc` instruction and make cpu mode monitor mode. In the monitor handler, I tried to changed stack pointer value...
  • armv7a/armv8 : Undefined Abort Exception and MMU
    Hi ! When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before...