• Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...
  • Cortex A53 : Cache policy setting
    Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
  • How to do cache invalid on Cortex-A53?
    hi,      I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.      Could you give me any suggestion about cache invalid? Thanks!     ...
  • Can Cortex-A53 be used in lock-step mode?
    Can Cortex-A53 be used in lock-step mode? There are many references for Cortex-R5 being used in lock step mode , could not find any information about Cortex-A53 , Can you please help
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...