• GIC-v3: optional asymetric / legacy support
    Hi, how can I check if the GIC-v3 I am using has support for the optional asymetric / legacy support ? Best, V.
  • Cortex-A9/GIC: de-activate an active interrupt
    Hi my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world. No...
  • Resetting GIC by SW?
    Hello, we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500. The M3 has access to all registers that...
  • GICv3: setting G1SEN / G1NSEN in GICD_CTLR
    During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS) and I got the surprise to see that the finale value...
  • AArch64/GICv3:ICC_SGI1R_EL1: AFF1
    I wonder, is AFF1 in ICC_SGI1R_EL1 also a bit-mask or does it address directly the cluster? So does AFF1 == 3 address cluster 3 or cluster 0 and cluster 1.