• Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • initialisation of DRAM ECC with Cortex A9 CPU
    Hello, I would like to find the most optimal method to initialize the DRAM ECC of my Xilinx Zynq7000 SoC. Zynq7000 SoC comprises a dual core Cortex A9 CPU with L1 data and and L1 instruction caches...
  • Document on difference between Cortex-A / -R / -M
    Hi experts, Is there any specific document on specifying the differences between Cortex-A/-R/-M series of processors.
  • ATCM ECC error causes prefetch abort despite ECC check being disabled.
    Hello, I am working with TI's TMS570LS3137 (ARM Cortex R4F). A certain part of my code consistently causes a prefetch abort (I say part because the exact location seems to vary slightly). To try...
  • Cortex-A53 - GICv4 Documentation
    i have 1 more query related to GIC. in Cortex-A53 it is mentioned that it is using GIC 400 and GIC architecture Version 4, but in ARM site i am not seeing any GIC V4 Doc, there is only GIc v2