• ARM Cortex A9 flush cache
    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements. Is it doable from user mode? Processor: ARM Cortex...
  • Cache cleaning and invalidating in ARM Cortex-A
    Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two...
  • System wide cache flush
    Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...
  • is it possible to flush/invalidate cache from user space for AARCH32
    Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...