• AXI4: Unaligned read transactions
    Hi guys, I'm new to the AXI ecosystem. However, I have one question related to unaligned read transfers. Does AXI4 support unaligned read transfers although er are no strobe lines? If so, which data on...
  • Problems with  AXI4  write data channel
    Hello:     Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel, When slave0 has received wvaild which...
  • AXI4: Wider transactions than BUS width allowed?
    Hi AXI-experts, Does AX4 support burst sizes larger than the bus width? Narrow transactions are allowed, but do wider transactions also work? Best regards, Robert
  • In read or write transaction in AXI.what happen if data transaction  is before address.
    HI there, I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking...
  • Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...