• making physical memory pages not cacheable (probabaly by modifying page table entry)
    I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
  • page table Cachability bit effect!
    Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
  • aarch64 kernel using aarch32 page tables
    Hi ! I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8. My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point...
  • ARM A64 Page table
    Hi, I have a question on ARM page table. I am running a bare metal application on Cortex A72 and i have a failure with my application. Upon debugging the failure, i found an address which is contributing...
  • Initial page table walk for secure/nonsecure accesses
    I have a basic concept question. From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups. So these can...