• Code for integer division on Cortex-A8?
    Hi all, when I wrote a C code with division operation the compiler is generating some library calls.....when I tried to see the equivalent code for those function calls...I'm unable to reach there (may...
  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?
    hi : I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*). however, I can not find any clue about flushing L2 cache to DRAM(if without L3).  and I saw some points that...
  • how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm file?
    how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm form? if there are some documents which describes it in detail? In Chinese: 我目前用cortex-A8(armV7)来开发项目...
  • Event counters take differing number of cycles
    We have some code that sets up various event counters and reads them.  We bracket this code with reads of the cycle counter.  We have noticed that depending on what event counter we are configuring, we...
  • How to Write CP15 registers (CRn:C15) in Non-Secure mode
    Some of the Cortex-A8 registers like CP15 registers (CRn:C15) are writeable only in secure mode. How to write these registers when the CPU is in Non-Secure mode? Please let me know if there is any reference...