• dsb and dmb
    Hi all: I have some questions about DMB and DSB in armv8. (1) In armv8 Reference Manual doc, it says " The DMB instruction does not ensure the completion of any of the memory accesses for which...
  • Data synchronization Barrier and cache.
    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
  • What is the difference of DMB and DSB instruction?
    Dear sirs, From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which...
  • Does DSB(SY) guarantee Write-combined write to be flushed?
    I found the following code sequence in our code. Can I know if the following DSB(SY) guarantees that register access (#3) will be executed after contents of #1 flushed to DDR memory? 1: write value...
  • The merit of data cache cleaning
    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message...