• The exact definition of outer and inner in ARMv7
    Hello, I'm reading ARMv7 architecture reference manual and there are the following keywords: outer cacheable inner cacheable outer sharable inner sharable It looks like that outer/inner...
  • why inner attribute is affected by outer configuration?
    Hi expert: I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1...
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?
    Hi, I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores. The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters...
  • Inner/Outer Cacheability in Cortex V8-R
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...
  • Inner/Outer share ability in Cortex R52
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...