• AMBA3 AXI - Exclusive access
    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location?? Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID...
  • AXI Atomic Access
    Hello, I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion. My question is: 1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates...
  • How to test atomic access implemented with Load Store Exclusive Assembly (LDREX / STREX)
    Hi there, i have several inline assembly functions wrapped in C. They implement atomic / read-modfy-write style Compare And Swap Increment Decrement Lock Semaphore Creating a good...
  • ARMv8: strongly ordered memory and exclusive access
    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core. While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly...
  • STREX always clears the exclusive access tag
    Hello everybody, Section 18.8 Exclusive access of Cortex-A Series Programmer's Guide says the following: STREX can be considered as a conditional store. The store is performed only if the physical address...