• instructions fetch
    Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
  • Disabling PFU / instruction pre-fetch on Cortex-R4?
    Hello, I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me: Determines if instructions can...
  • What will happen if Cortex-M0 fetches 0xFFFF_FFFF as an instruction ?
    Dear Guys,     In typical SoC product, the FLASH memory is initially empty after being shipped from factory, in which the data are all "0xFFFF_FFFF".     I am curious how Cortex-M0 deals with the undefined...
  • Instruction Fetches from Peripheral Memory Space
    Is it possible to use the MPU to configure the Peripheral Memory Space as Execute? It looks possible via the MPU_RBAR.XN bit. If this is the case, is it fair to say that TrustZone aware select gates...
  • Experimentation of Dual Issue
    Hi all, Can somebody specify asm code to experiment the dual issue of instructions and how the processor executes parallely ? Also i tried like performing LDM instruction followed by LSL instruction....