• Significance of the WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • AXI Locked Write and Lock Scope
    Hi All,        1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • AXI FIXED burst ; Wr/Rd narrow transactions.
    1. I'm examining AXI burst of FIXED type. 2. Data bus width is of 128bit. 3. case scenario WRITE :     awlen    = 2 (3 write transfers)     awsize  = 2 (32bit per each transfer)     awburst = 0 (FIXED...
  • AXI Write Access: WLAST/WVALID handling
    Can I set WLAST high while WVALID is low? The AXI specification is not clear at this point.