• Introducing the next generation of AXI and ACE protocols
    Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols...
  • Difference in AxCACHE signal values in AXI protocol
    Hello, I am new to AXI. Where should I lookout for information on awcache signal. The protocol has various cache transfers. What is the difference between each of them? Where can I lookout for this...
  • axi problem
    Hi All I have two questions. Q1: is it ok that WVALID , WREADY and BVALID assert at the same cycle? Thanks! Q2: what is different between out of order and data interleaving ? Thanks!
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • axi ordering
    Hi the master is connected to axi-interconnect and two slaves(A and B) are connected to axi-interconnect. The master send a write transcation(AA) to slave A and then send a write transcation(BB) to slave...