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  • ARM A64 Page table
    Hi, I have a question on ARM page table. I am running a bare metal application on Cortex A72 and i have a failure with my application. Upon debugging the failure, i found an address which is contributing...
  • Invalid entry - mmu page tables
    Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
  • making physical memory pages not cacheable (probabaly by modifying page table entry)
    I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
  • Share aarch64 page tables created by Linux with SMMU
    Hello! I am currently working on creating a shared virtual address space in Linux arm64 on a Xilinx Zynq Ultrascale+ board. In the future it should be possible to share pointers/addresses between the...