• cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • How can I get the number of non-cacheable access in CA-55?
    The PMU of CA-55 can not count non-cacheable access event. L1I_CACHE_ACCESS and L1D_CACHE_ACCESS does not count non-cacheable access. I want to distinguish cacheable access and non-cacheable access...
  • Cache type and cache operation sequence
    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC. SW on each execution units (A and B) Reads and Writes to this shared...
  • Data synchronization Barrier and cache.
    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...