• Data Abort Exception in A53
    Hello, I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU...
  • ARM Cortex-A53 System Register
    Hello, I wanted to check the value of following interrupt related registers i.e. ICC_IAR1_EL1 ICC_EOIR1_EL1 I'm able to find the ICC_IAR1_EL1 inside the CORTEXA53 hierarchy. But NOT able to...
  • Program MPS2+ directly with Quartus programmer
    Is it possible to directly program the FPGA in the MPS2+ board with the Altera Quartus Programmer? As far as I understand is the MPS2+ 10 Pin FJTAG port not compatible to the Alter USB blaster. Is...
  • [Cortex-A53] STP instruction stores out of the specified memory
    Hi Experts, I have a question about "STP" instruction in Cortex-A53. STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted. I don't know why cause it....
  • Ways to Tx data from Cortex R5 to A53?
    Hello, I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some...