• CA72 transactions IDs
    In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores. But in CA72, I can't find such descriptions...
  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?
    Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is:...
  • Can Cortex-A53 l2 cache be controlled seperatly?
    Hi Experts, I'm researching Cortex-A53 cache. Can Cortex-a53 l2cache be enable/disable independently? Is it possible to only enable l1 cache and disable l2cache? Does cortex-a53 support l2cache...
  • Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...
  • Multi core L1 cache coherent
    Dear experts, I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation. Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached)...