• Penalty estimate of TLB miss or table walk in armv8
    Hello! Is there are rough estimate oh what would be the penalty for each tlb miss or table walk for different table levels? And what are the factors that can determine the deviation between each measurement...
  • Initial page table walk for secure/nonsecure accesses
    I have a basic concept question. From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups. So these can...
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...
  • interrupt distribution on A53 processor
    Hi, Linux Kernel 4.9 Processor a53 SMP 64 Bit linux image Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts. moving...
  • What is the value of a license of an ARM Cortex-A53 processor?
    I would like to know the price of the license or terms for each core Cortex-A53 and the price of a 4-core processor Cortex-A53 is charged. Sorry if misspelled not know much English and I'm writing with...