• cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • ARMv6 performance monitor: Can I record the instruction which caused the data cache miss
    Hi, I'm new to community. I am recently working on cache performance evaluation of a software on arm ( which I did not know much about before) and aiming  to record all the instructions causing a data...
  • A TCM problem
    Hi all Here is a problem about the using of TCM. I put two functions(they are just the same) of time-delay in the ITCM and the normal RAM, using the scatter file, and execute them one after another. But...
  • Is there enough processing horsepower in the ARM1176 processor ....
    .... to take a 200 kHz digital pulse train input and turn it in to a 41.7 kHz output pulse train? I want to use an ISR to detect the rising edge of a pulse train, determine if it is time to output a pulse...
  • Arm11 clock
    Note: This was originally posted on 13th October 2008 at http://forums.arm.com Hello, Does anyone know if there is a timestamp clock in Arm? Something like the RDTSC in intel? Or some other high frequency...