• How cortex-M4 handles data hazard situations in the pipeline?
    Hello to all, Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline. Is the processor...
  • TCM arbitration hazard: Considerations for Firmware
    According to the ARM spec (ARM DDI 0460D section 8.4.4): TCM arbitration Each TCM port receives requests from the LSU, PFU, and AXI slave. In most cases, the LSU has the highest priority, followed...
  • Understanding XDMAC on Cortex-M7
    I've inherited some XDMAC code and no one that wrote this code really seems to be able to explain anomalies that I am seeing. So, I'm trying to understand just the basics in an attempt to make sure it...
  • How to acknowledge/clear active interrupt in Cortex-M4
    Hi all, I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to...
  • Understanding interrupt latency and jitter in Cortex-M
    Hi, I've been trying to get a good grasp of the variables associated with interrupt handling in the Cortex-M family. I've read " A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the...