• Elba - Bringing it all together
    In the previous three blogs (Parts 1 , 2 and 3 ) I've outlined the background and key decisions involved in the development and implementation of the Elba testchip.  Now we'll look at the final steps...
  • MSP & PSP - 'Using it All'
    As I understand it, if, when my system boots and I switch to using PSP (process stack pointer) and allow the CPU to handle exceptions using MSP? Have I got that the right way around? The reason is that...
  • Fail to run the compiled MPS2+ project
    Hi, After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA. While the already downloaded image that arrives on the FPGA runs fine...
  • Can I run an A9 program under A53 without any modification
    I have an electrical product which is controlled by ARM A9 CPU(linux 3.15+control program). Now I plan to upgrade the CPU from A9 to A53 and rebuild the linux 3.15. Is it possible that the control...
  • Running two bare-metal programs on two separate cores in Cortex-A9
    Hello, I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache...