• cortex M33 multicore debug resources
    As I reading the debugging in the Armv8-M manual, I found that there is little description of the multicore system. The debug resources have a specific address range. It is acceptable in a single-core...
  • IMPRECISERR on Cortex-M33 r0p3
    Hi, I just wanted to double-check, that IMPRECISERR (BFSR part of CFSR register ) is by default not implemented in Cortex-M33 (as mentioned here ). The reason I am asking is that on a different page...
  • Arm Musca A1 - SRAM0 MPC Security attribute during boot
    Hi all, I am using Arm Musca-A1 in a project and I'm getting a strange behavior on the MPC connected to the internal SRAM0. During boot, I am loading some data to SRAM0 (S region). While when I access...
  • Software interrupt generation on Cortex M33.
    Hi, On Cortex M33 , i am trying to check software interrupt functionality. Below is the CMSIS APIs i used. Note that the CPU is in secure world and secure VTOR is being configured. Also, ITNS config...
  • Cortex M33 Tracing
    Hey, As I am exploring the tracing capabilities present in the Cortex M33, there are some things that I am not able to understand fully, such as the connection between ETM and the tracing sinks. As...